This disclosure relates to a semiconductor integrated circuit including internal circuit and a protection circuit configured to protect the internal circuit from over-voltages higher than an operation voltage of the internal circuit. This invention also relates to a method of protecting the semiconductor integrated circuit from the over-voltage.
Over-voltages applied to a connection terminal of a semiconductor integrated circuit include those caused by electro-static discharge (ESD) and by electrical over-stress (EOS).
ESD is a phenomenon in which static electricity charged in a human body or the like is applied to a connection terminal of the semiconductor integrated circuit. As shown in FIG. 14, this causes a surge current of the order of several amperes to flow through the semiconductor integrated circuit for a short period of time of, for example, 1 μs or less.
EOS is a phenomenon that occurs when a ground of the semiconductor integrated circuit is separated from that of a tester used for testing the semiconductor integrated circuit. For example, during the rise of a power supply voltage of the semiconductor integrated circuit, a power supply voltage of 10 V to 20 V is applied to a connection terminal of the semiconductor integrated circuit for a relatively long period of time of, for example, several milliseconds to several seconds, as shown in FIG. 15.
ESD is caused by sudden discharge of electric charge, and its voltage rises in a pulse-like manner in a period of time shorter than that for EOS. EOS has a rise time longer than that of ESD and its voltage lasts for a longer period of time.
The semiconductor integrated circuit is usually equipped with an ESD protection device that turns on and discharges the over voltage. The ESD protection device may also turn on when EOS is applied. Then, a current of the order of amperes flows through the ESD protection device for several milliseconds to several seconds and may damage the ESD protection device. As a solution to this problem, U.S. Pat. No. 5,654,574 (Patent Document 1) proposes an ESD/EOS protection circuit that is equipped with separate protective measures against ESD and EOS, respectively.
FIG. 16 is a diagram illustrating an ESD/EOS protection circuit proposed in Patent Document 1.
An ESD/EOS protection circuit 200 illustrated in FIG. 16 includes high-voltage depletion type metal oxide semiconductor field-effect transistors (MOSFETs) 201 and 202 having parasitic diodes 201a and 202a, respectively. A gate and a source of the MOSFET 201 are connected in common to a connection terminal 203. A gate and a source of the MOSFET 202 are connected in common through a resistor 204 to an internal logic 210. Drains of the MOSFETs 201 and 202 are connected to each other and further connected to a cathode of a first diode 205. An anode of the first diode 205 is connected to a ground GND. A cathode of a second diode 206 is connected to a connection point between the resistor 204 and the internal logic 210. An anode of the second diode 206 is connected to the ground GND.
In a normal operating state of the semiconductor integrated circuit, the MOSFETs 201 and 202, both of which are depletion type MOSFETs, are in the ON state. Therefore, a signal input to the connection terminal 203 is transmitted through the path including the MOSFET 201, MOSFET 202, and the resistor 204 to the internal logic 210. In the normal operating state, because a potential of a signal supplied to the connection terminal 203 is low, the first and second diodes 205 and 206 are in the OFF state.
Increasing the voltage applied to the connection terminal 203 increases a reverse bias voltage of the first and second diodes 205 and 206, and causes the first and second diodes 205 and 206 to break down. Breakdown voltages Vt_rev1 and Vt_rev2 of the first and second diodes 205 and 206 are set such that a relationship of Vt_rev1>Vt_rev2 is satisfied.
Operations performed in the ESD/EOS protection circuit 200 when ESD is applied and when EOS is applied will be described.
FIG. 17 is a diagram for describing an operation performed in the ESD/EOS protection circuit 200 of FIG. 16 when ESD is applied. An ESD pulse that exceeds the breakdown voltage Vt_rev1 of the first diode 205 is applied to the connection terminal 203 illustrated in FIG. 17. This turns on, or breaks down, the first diode 205 and allows a surge current Iesd to flow through the current path including the MOSFET 201 and the first diode 205 to the ground GND.
FIG. 18 is a diagram for describing an operation performed in the ESD/EOS protection circuit 200 of FIG. 16 when EOS is applied. As an EOS voltage, a voltage between the breakdown voltage Vt_rev1 of the first diode 205 and the breakdown voltage Vt_rev2 of the second diode 206 is applied to the connection terminal 203. Because the relationship Vt_rev1>Vt_rev2 is satisfied, applying the EOS voltage turns on the second diode 206 only, and allows a current Ieos to flow through the current path including the MOSFET 201, the MOSFET 202, the resistor 204, and the second diode 206 to the ground GND.
Thus, as described above, the ESD/EOS protection circuit 200 is equipped with separate protective measures against ESD and EOS, respectively.
However, in the ESD/EOS protection circuit 200 proposed in Patent Document 1, an EOS voltage greater than the breakdown voltage Vt_rev1 of the first diode 205 may be applied to the connection terminal 203.
FIG. 19 is a diagram for describing an operation performed in the ESD/EOS protection circuit 200 of FIG. 16 when an EOS voltage greater than the breakdown voltage Vt_rev1 of the first diode 205 is applied. Applying such an EOS voltage turns on the first diode 205. Because the first diode 205 is configured to allow a surge current caused by ESD to flow, turning on the first diode 205 causes a large current to flow through the first diode 205. In other words, applying an EOS voltage greater than the breakdown voltage Vt_rev1 of the first diode 205 to the connection terminal 203 may damage the first diode 205, which is provided as an ESD protection device in the ESD/EOS protection circuit 200.
Increasing the breakdown voltage Vt_rev1 of the first diode 205 would decrease the risk of damaging the first diode 205. However, increasing the breakdown voltage of the first diode 205 may degrade the protection ability of the ESD/EOS protection circuit 200 against ESD. Additionally, because the breakdown voltages depend on the semiconductor manufacturing process, it is not easy to reduce variations of the breakdown voltages of the diodes among products.